1. Field of the Invention
The present invention relates to an output buffer circuit for outputting digital signals.
2. Description of the Related Art
In the present market for semiconductor integrated circuits, the consuming public has increasingly demanded circuits having faster operational speeds with lower power requirements. This demand is mirrored by a similar demand placed on the design of widely used semiconductor component circuits. One such component circuit is the output buffer circuit.
FIG. 1 shows one example of a conventional output buffer circuit. An N channel MOS transistor Tr1 has a drain connected to an output terminal "To" and a source connected to a ground GND. An input signal IN is input to the gate of the transistor Tr1 from a logic control circuit 1. In such an open-drain type output buffer circuit, the transistor Tr1 is turned on and outputs an L-level output signal OUT from the output terminal "To" when the input signal IN goes high. Transistor Tr1 turns off to render the output signal OUT to a high impedance state when the input signal IN goes low. Connected to the output terminal "To" is a load circuit 2a operating according to whether the output signal OUT is at a L level or at a high impedance state.
The load circuit 2a has a high-resistance resistor R whose first end is connected to the output terminal "To" with a power source Vcc connected to its second end. When the transistor Tr1 is turned on, a drain current flows via the resistor R to the transistor Tr1 from the power source Vcc. As a result, the output signal OUT goes low based on a voltage drop caused by the resistor R. When the transistor Tr1 is turned off, a drain current to the transistor Tr1 from the power source Vcc stops. As a result, the output signal OUT from the load circuit has a high impedance. As a result, current is supplied via the resistor R to the output terminal "To" from the power source Vcc, setting the potential of the output terminal "To" to an H level.
In this output buffer circuit, a rise in the potential of the output signal OUT when the transistor Tr1 switches off depends on the resistance of the resistor R. When the resistance of the resistor R is large, the rate of change in the rising speed of the output signal OUT decreases. When the resistance of resistor R is small, and when rate of change in the rising speed of output signal OUT increases, the drain current of the transistor Tr1 increases. This causes an increase in the power consumed by the circuit when an L-level output signal OUT is output.
To overcome such a shortcoming, a tri-state type output buffer circuit as shown in FIG. 2 has been proposed. This output buffer circuit comprises an N channel MOS transistor Tr2 as a pull-up side transistor, and an N channel MOS transistor Tr3 as a pull-down side transistor. The drain of the transistor Tr2 is connected to a high-potential power source Vcc, the source of the transistor Tr2 is connected to an output terminal "To", as well as the drain of the transistor Tr3. The source of Tr3 is connected to the ground GND as a low-potential power source. Input signals IN1 and IN2 are input respectively to the gates of the transistors Tr2 and Tr3 from a logic control circuit 1. In this output buffer circuit, when the input signal IN1 goes low and the input signal IN2 goes high, the transistor Tr2 is turned off and the transistor Tr3 is turned on, setting the output signal OUT to an L level. When the input signal IN1 goes high and the input signal IN2 goes low, the transistor Tr2 is turned on and the transistor Tr3 is turned off. This in effect sets the output signal OUT to an H level. When both input signals IN1 and IN2 go low, the transistors Tr2 and Tr3 are both turned off, setting the output signal OUT in a high impedance state.
Connected to the output terminal "To" of this output buffer circuit is a load circuit 2b which functions based on whether the output signal OUT is an L level, an H level or in a high impedance state. The load circuit 2b has terminal resistors Ru and Rd whose first ends are connected to the output terminal "To". The second end of the resistor Ru is connected to a power source Vcc and the second end of the resistor Rd connected to the ground GND. When the transistor Tr3 is turned off and the transistor Tr2 is turned on, the drain current of transistor Tr2 flows via the resistor Rd to the ground GND. As a result, the output signal OUT goes high based on a voltage drop caused by the resistor Rd. When the transistor Tr2 is turned off and the transistor Tr3 is turned on, the drain current flows into the transistor Tr3 via the resistor Ru from the power source Vcc. As a result, the output signal OUT goes low based on a voltage drop caused by the resistor Ru. When the transistors Tr2 and Tr3 are turned off, the output signal OUT is output at high impedance, so that the potential of the output terminal "To" is obtained by dividing the potential difference between the power source Vcc and the ground GND by the resistors Ru and Rd. Since the transistor Tr2 is turned on at the time when output signal OUT rises from a L level, the level of the output signal OUT can be pulled up to the H level from the L level quickly without reducing the resistance of the resistor Ru. If the transistors Tr2 and Tr3 are turned off after the potential of the output signal OUT is pulled up, the output signal OUT goes to a high impedance state so that the potential at the output terminal "To" promptly converges to a predetermined potential set by the resistors Ru and Rd. Further, because there is no need to decrease the resistance of the resistor Ru, the drain current of the transistor Tr3 is prevented from increasing when the L-level output signal OUT is output, thus preventing an increase in consumed power.
However, when output signal OUT is switched from an L to an H level in the output buffer circuit as shown in FIG. 2, the transistor Tr2 remains turned on. Consequently, the drain current of the transistor Tr2 flows to the ground GND via the resistor Rd of the load circuit 2b. This causes an increase in the power consumed by the circuit. When the output terminal "To" is coupled to the ground GND via the load circuit 2b with the transistor Tr2 turned on, current flows to the ground GND via the transistor Tr2 from the power source Vcc. This causes a further increase in the power consumed by the circuit.